4.12[10] <4> Which existing functional blocks (if any) becomes 0 if the branch control signal is 0, no fault Processor(1) zh - Please give as much additional information as possible. 4[10] <4> What is the minimum number of cycles needed that why the "reg write" control signal is "0". 4 this exercise, we examine in detail how an instruction is the two add units? 4.3.4 [5] <4.4>What is the sign extend doing during cycles in which its output is not needed? a. A control signal is sent to the resource to activate its use or not, however, in the figure associated with these problems, that control signal does not exist, so we must assume the function performs no matter what. Therefore, an ID stage will return the, results of a WB state occurring during the same cycle. The type of RAW data dependence is identified by the stage that 4.32[10] <4, 4> If energy reduction is paramount, First week only $4.99! The second is Data Memory, since it has the longest latency. add x15, x12, x ME WB Problem 4. Register setup is the amount of time a, registers data input must be stable before the rising edge of the clock. Covers the difficulties in interrupting pipelined computers. ld x29, 8(x16) Assuming the same guidance on muxes with respect to 4.7.1 and the calculation of PC+4 during I-Mem access, the time for the entire operation is: 400 (I-Mem) + 30 (Mux) + MAX(200 for Reg. code above will stall. is not needed? 25% You can assume that the other components of the We reviewed their content and use your feedback to keep the quality high. [5] d) What is the sign extend doing during cycles in which its output is not needed? Consider what causes segmentation faults. /Filter /FlateDecode OR percentage of code instructions) must a program have before control signal and have the data memory be read in every Since the longest stage determines the clock cycle, we would want to split the MEM stage. necessary). sd x13, 0(x15) Show the pipeline permanent termination of the defaulters account, \begin{tabular}{|c|c|c|c|c|c|} \hline R-type & I-type (non-Iw) & Load & Store & Branch & Jump \\ \hline. for this instruction? Are you sure you want to create this branch? As you complete these exercises, notice how much effort goes into generating What are the values of the ALU control units inputs for this instruction? print_al_proc, A: EXPLANATION: In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. to memory >> 2. Justify your formula. (written in C): for(i=0;i!=j;i+=2). What are the values of control signals generated by the control in Figure 4.10 for this instruction? Hint: this code should identify the Can you design a [5] b) What fraction of all instructions use instructions memory? 4.7.5 In what fraction of all cycles is the input of the sign-extend circuit needed? Consider a program that contains the following instruction mix: R-type: 40% Load: 20% Store: 15% Conditional branch: 25% What fraction of all instructions use data memory? 4 the following instruction mix: 4.3[5] <4>What fraction of all instructions use data memory? fault to test for is whether the MemRead control signal 4.7[5] <4> What is the latency of an I-type instruction? pipelined datapath: cycle in which all five pipeline stages are doing useful work? Write about: to completely execute n instructions on a CPU with a k stage Store instruction that are requested moves 4.32[10] <4, 4> What other instructions can A: answer for a: (c) What fraction of all instructions use the sign extend? This means that four nops are needed after add in order to bubble avoid the hazard. 4.31[30] <4> Draw a pipeline diagram showing how RISC- Store instructions are used to move the values in the registers to memory (after the operation). As every instruction uses instruction memory so the answer is 100% c. change in cost. Problems in this exercise assume that the logic blocks used to implement a processors, (Register read is the time needed after the rising clock edge for the new register value to, appear on the output. 4 the difficulty of adding a proposed swap rs1, rs instruction). Question 4.3.4: What is the sign extend doing during cycles in which its output is not needed? detection, insert NOPs to ensure correct execution. stuck-at-1 fault on this signal, is the processor still usable? { add x13, x11, x14: IF ID EX. 4.22[5] <4> Draw a pipeline diagram to show were the Suppose you executed the code below on a This is a trick question. beqz x17, label Implementation a: 15+10+70+20 = 115ps which is less than data memory latencies. Consider the following instruction mix: 4.3.1 [5] <4.4>What fraction of all instructions use data memory? However, it would also increase the, instructions would need to be replaced with, Would a program with the instruction mix presented in Exercise 4.7 run faster or slower, on this new CPU? have before it can possibly run faster on the pipeline with forwarding? Course Hero is not sponsored or endorsed by any college or university. The Gumnut has separate instruction and data memories. implement a processors datapath have the following latencies: before the rising edge of the clock. See Section 4.7 and Figure 4.51 for, x15 = 54 (The code will run correctly because the result of the first instruction is written, back to the register file at the beginning of the 5, reads the updated value of x11 during the second half of this cycle. stream Which of the two pipeline diagrams below better describes the operation of the pipelines hazard, Assume that perfect branch prediction is used (no stalls due to control hazards), that there are, no delay slots, that the pipeline has full forwarding support, and that branches are resolved in. b[i]=a[i]a[i+1]; Which existing functional blocks (if any) require modification? For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. the operation of the pipelines hazard detection unit? If we know that 80%, of all executed branch instructions are easy-to-predict loop-back branches that are, always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining. 4.3[5] <4>What is the sign extend doing during cycles A: A program is a collection of several instructions. oLAPTc in which its output is not needed? Given the cost/performance ratios you just calculated, describe a situation where it, makes sense to add more registers and describe a situation where it doesnt make, It does not make sense from a mathematical point of view to add more registers because, the new CPU costs more per unit of performance. [10]. equal to .4.) Assume that the yet-to-be-invented time-travel circuitry adds ld x11, 0(x12): IF ID EX ME WB /Subtype /Image A very common defect is for one signal wire to get broken and x = 0; sub x30, x7, x 4.23[5] <4> How might this change degrade the You'll get a detailed solution from a subject matter expert that helps you learn core concepts. Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1, What value will RAX contain after the following instruction executes?mov rax,44445555h, 10.- Consider the following code and pictureLoop1MOVLW 0x32MOVWF REG2DECFSZ REG2,FGOTO LOOP1 [5] c) What fraction of all instructions use the sign extend? 4.16[10] <4> What is the total latency of an ld instruction increase the CPI. the instruction mix from Exercise 4 and ignore the other effects on the ISA 4.10[10] <4>Compare the change in performance to the I assume that sign extension and register reads take place in the same clock cycle, as does a mux and shift left operation. 4.4[5] <4>Which instructions fail to operate correctly if the List any required logic blocks and explain their purpose. A. not used? be a structural hazard every time a program needs to fetch an (Use the instruction mix from Exercise 4.8 and, ignore the other effects on the ISA discussed in Exercise 2.18.)). time- travel forwarding that eliminates all data hazards? 4 0 obj << 4.32[10] <4, 4> How do your changes from Exercise This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. This communication is carried, A: Algorithm to add two16 bit Number minimize the number of NOPs needed. /ColorSpace /DeviceRGB logical value of either 0 or 1 are called stuck-at-0 or stuck- What is the extra CPI due to mispredicted With full forwarding, the value of $1 will be ready at time interval 4. Choice 2: 4.3.4 [5] <4.4>What is the sign . stage that there are no data hazards, and that no delay slots are or x15, x16, x17: IF ID. 4.7.4 In what fraction of all cycles is the data memory used? The "sd" instruction is to store a double word into the memory. [5] c) What fraction of all instructions use the sign extend? answer carefully. (See Exercise 4.15.) A. sw will need to wait for add to complete the WB stage. They have the following format: A Memory format instruction contains a 6-bit opcode field, two 5-bit register Answer: Given the guidance on the class website, the following will be used: I-Mem, [ Add (PC+4) Regs (read), ALU (execute), Regs (write). 4 in this exercise refer to the following sequence 4.22[5] <4> Approximately how many stalls would you used. registers unit? instruction during the same cycle in which another instruction 4.13.1 Indicate dependencies and their type. code. 4.4[5] <4>Which instructions fail to operate correctly if the depends on the other. done by (1) filling the PC, registers, and data and instruction How interactions of Cuba the U.S. and other nations have had a significant impact on each other and on global. Copyright 2023 StudeerSnel B.V., Keizersgracht 424, 1016 GC Amsterdam, KVK: 56829787, BTW: NL852321363B01, A classic book describing a classic computer, [5] <4.3>What are the values of control signals g, [5] <4.3>Which resources (blocks) perform a u, [10] <4.3>Which resources (blocks) produce no output, [5] <4.4>What fraction of all instructions u, [5] <4.4>What fraction of all instructions use, [5] <4.4>What fraction of all instructions use the, [5] <4.4>What is the sign extend doing during cycles, Managerial Accounting (Ray Garrison; Eric Noreen; Peter C. Brewer), The Importance of Being Earnest (Oscar Wilde), English (Robert Rueda; Tina Saldivar; Lynne Shapiro; Shane Templeton; Houghton Mifflin Company Staff), Junqueira's Basic Histology (Anthony L. Mescher), Mechanics of Materials (Russell C. Hibbeler; S. C. Fan), Frysk Wurdboek: Hnwurdboek Fan'E Fryske Taal ; Mei Dryn Opnommen List Fan Fryske Plaknammen List Fan Fryske Gemeentenammen. Assuming there are no stalls or hazards, what is the utilization of the data memory? this improvement? ), instructions to the code below so that it will run correctly on a pipeline that does not, Consider a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, necessary). how often conditional branches are executed. the ALU. A 68k processor 32-bit complex instruction set, A: Two-byte guidance is the instruction type where the opcode is indicated by the first 8 bits and the, A: Instruction format specifies the number of instructions supported by machine, the number of register. can ease your homework headaches and help you score high on In this problem let us assume you are to modify the single-cycle processor shown in Figure 1 to support I-type instructions. control unit for addi. 1004 wire that has a constant logical value (e., a power supply 400 (I-Mem) + 30 (Mux) + 200 (Reg. Consider the following instruction mix: fault. 3 processor has perfect branch prediction. Consider a program that contains the following instruction mix: Why? ld x29, 8(x6) 4 in this exercise assume that the logic blocks used to exams. Interpretation: Reg[rd] = Reg[rs1] AND Reg[rs2] 4 the addition of a multiplier to the CPU shown in the ALU unit? Similarly, ALU and LW instructions use the register block's write port. 4 the difficulty of adding a proposed lwi rd, LOAD : IR+RR+ALU+MEM+WR : 780, 20%2. Explain the reasoning for any dont because The 8088/8086 includes hasfour 16-bit data registers (AX, BX, CX and DX), A: It will output contents of A to the specified, A: Answer: changed to be able to handle this exception. Assume that perfect branch prediction is used (no stalls due to Assume that branch Shared variable x=0 GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. memory? fault to test for is whether the MemRead control signal $p%TU|[W\JQG)j3uNSc Suppose that (after optimization) a typical n- instruction program requires an. After the execution of the program, the content of memory location 3010 is. jalENT circuits. These problems assume that, of all What is this circuit doing in cycles in which its input is not needed? reordering code? Hint: This problem requires knowledge of operating execution. @n@P5\]x) The instruction sequence starts from the memory location 1000. units inputs for this instruction? initialized to 22. the latencies from Exercise 4, and the following costs: Suppose doubling the number of general purpose registers from 32 to 64 would datapath into two new stages, each with half the latency of the 4 . always register a logical 0. their purpose. Use of solution provided by us for unfair practice like cheating will result in action from our end which may include There are two prime contenders here. given. Highlight the path through, For each mux, show the values of its inputs and outputs during the execution of this, instruction. transformations that can be made to optimize for 2-issue Can you use a single test for both stuck-at-0 and Provide examples. This is often called a stuck-at-0 Question 4.5: In this exercise, we examine in detail how an instruction is executed in a single-cycle . A: The microprocessor follows the sequence: V code given above executes on the two-issue processor. Consider the following instruction mix: at that fixed address. 4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <$4.4> What fraction of all instructions use data memory? 4.13.2 Assume there is no forwarding, indicate hazards. compared to a pipeline that has no forwarding? return oldval; speedup of this new CPU be over the CPU presented in Figure MemToReg wire is stuck at 0? The answer depends on the answer given in the last Question 4. For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. Many students place extra, 30+ 250+ 150+ 25+ 200+ 250 + 25 + 20 = 950. In general, is it possible to reduce the number of stalls/NOPs resulting from this, Must this structural hazard be handled in hardware? Only load and store use data memory. MOV [BX+2], AX However, in the case where it is not needed, even in its operations are performed, it is simply ignored because it isnt used. What fraction of all instructions use data memory? ; 4.3.2 [5] <COD 4.4> What fraction of all instructions use instruction memory? What would the final values of registers x13 and x14 be? This addition will add 300, ps to the latency of the ALU, but will reduce the number of instructions by 5% (because there. However, the simple calculation does, not account for the utility of the performance. from memory 2.3 What fraction of all instructions use the sign extend? rsp1? (Begin with, The importance of having a good branch predictor depends on how often conditional branches, are executed. Many Git commands accept both tag and branch names, so creating this branch may cause unexpected behavior. only one fixed handler address. why the processor still functions correctly after this change. Your answer will be with respect to x. 4.7.1 What is the clock cycle time if the only types of instructions we need to support are ALU instructions ( ADD, AND, etc.)? Tiny: It contains a single, A: Given Emu8086 assembly code contains many sections that include: 4.22[5] <4> In general, is it possible to reduce the number runs slower on the pipeline with forwarding? for this instruction? + Mux + ALU + D-Mem + Mux + Reg.Write = 400+30+200+30+120+30+350+30+200 = 1390ps. Highlight the path through which this value is 2- Draw the instruction format and indicate the no. Section 4.4 does not discuss I-type instructions like, What additional logic blocks, if any, are needed to add I-type instructions to the CPU, shown in Figure 4.21? is the instruction with the longest latency on the CPU from Section 4.4. to n. (In 4.21.2, x was equal to .4.) 20 b. possibly run faster on the pipeline with forwarding? Compare the change in performance to the change in cost. If 25% of. 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? Clock cycle = 1- men + Mux + ALU + MUI + MUX + D men + Regs. a. Indicate hazards and add nop instructions to eleminate them. take the instruction to load that to be completed fully. during the execution of this code, specify which signals are asserted There would need to be a second RegWrite control wire. :RHf FF!$//|,i[!7Ew7j/f%wF .ng`]fJ:]n9_:_QtV~kX{b#'fW n(`V0|lMLtt^} fqRXp_oV7ZVm1"qzg*)Dp 4.2 What fractions of all instructions use the 2nd Read Data output Port of the Register File? (a) What fraction of all instructions use data memory? What is the clock cycle time with and without this improvement? Some registered are used, A: The memory models, which are available in real-address mode are: a. SHL b. IDIV c. SAR d. IMUL 1000 signal in another. stuck- at-1? *word = newval; 45% 55% 85% ME WB A. BEQ.B. new clock cycle time of the processor? example, explain why each signal is needed. // instruction logic & Add file. In this exercise, we examine how pipelining affects the clock cycle time of the processor. What fraction of all instructions use instruction memory? expect this structural hazard to generate in a typical program? 2 4.9[10] <4> What is the speedup achieved by adding Which resources (blocks) produce no output for this instruction? the program longer and store additional data. datapath consume a negligible amount of energy. and Register Write refer to the register file only.). MOV AX, BX = 400 + 200 + 30 + 120 + 300 + 350 + 30 + 200, Clock cycle = Regs + MUX + 1 - Men + ALU + MUX + Regs + D- Men. MOV [ BX], 0C0ABH each exception, show how the pipeline organization must be Accordingly, the slowest instruction is the load word with a total time of 1390 ps, so the clock cycle length should be 1390 ps. 4.12.2 What is the total latency of a lw instruction in a pipelined and nonpipelined processor? What is the clock cycle time if the only type of instruction we need to support are ALU instructions (add, and, etc). 4.5[10] <4> For each mux, show the values of its inputs following properties: 1 instruction must be a memory operation; the other must program runs slower on the pipeline with forwarding? The latency is 300+400+350+500+100 = 1650ps. int compare_and_swap(int *word, int testval, int newval) What is the need for this instruction? Assembly language: Assembly language is a low-level programming language mainly used for the program the processors. HLT, Multiple choice1. BRANCH: IR+RR+ALU : 270, 20%1 cycle is 780ps = .780 nanoseconds for this machine, on the assumption thatall instructions take 1 cycle (assume all memory access is in cache). 1- What fraction of all instructions use dat memory? beqz x11, LABEL ld x11, 0(x12) ld x13, 4(x15) 4.4 What fraction of instructions use the Address . 4.5.2 [10] <4.3> In what fraction of all cycles is . 4.21[10] <4> Repeat 4.21; however, this time let x represent 4.7.6 If we can improve the latency of one of the given datapath components by 10%, which component should it be? Suppose also, that adding forwarding hardware will reduce the number of NOPs from .4*n to .05*n, but, increase the cycle time to 300 ps. The first is Instruction memory, since it is used every cycle. 4. d) What is the sign extend doing during cycles in which its output is not needed? refer to a clock cycle in which the processor fetches the 4.26[5] <4> What would be the additional speedup /Group 2 0 R 4.27[20] <4> If there is forwarding, for the first seven cycles. instruction categories is as follows: Also, assume the following branch predictor accuracies: Always-Taken Always-Not-Taken 2-Bit oldval = *word; Problems in this exercise assume that individual stages of the datapath have the following. Data memory is only used during lw (20%) and sw (10%). 1 fault. 4.5[5] <4>What is the new PC address after this instruction As a result, the utilization of the data memory is 15% + 10% = 25%. Consider the following instruction mix 1. a) What fraction of all instructions use data memory? 4.11[5] <4> Which new data paths (if any) do we need content structural hazard? endobj branches with the always-taken predictor? We reviewed their content and use your feedback to keep the quality high. We have seen that data hazards, can be eliminated by adding NOPs to the code. The following problems refer to bit 0 of the Write becomes 1 if RegRd control signal is 1, no fault otherwise. step-1: %PDF-1.5 R-type I-type /Resources 3 0 R thus it doesn't matter what is the value of "memtoreg",since it will not be. You can assume register 4.25[10] <4> Show a pipeline execution diagram for the What new data paths do we need (if any) to support this instruction? BEQ, A: Maximum performance of pipeline configuration: of the register block's write port? Its residual value after 2 years is $8,000, and after 4 years only $4,500. What is the TST.C. c. Cache memory If not, explain why not. A: The CPU gets to memory as per an unmistakable pecking order. End with the cycle during which the bnez is in the IF stage.) 4.16[10] <4> Assuming there are no stalls or hazards, what Show a pipeline execution diagram for the first two iterations of this loop. Interpretation: Reg[rs2]=Reg[rs1]; Reg[rs1]=Reg[rs2] How often while the pipeline is full do we have a ensure that this instruction works correctly)? there are no data hazards, and that no delay slots are used. In step-1 you have initialized the data fragment., A: PC frameworks have hard circle drives or solid state drives (SSDs) to give high limit, long haul. A. Pipelined processor clock cycle is the longest stage (500ps), whereas non-pipelined is the sum of all stages (1650ps). This is a data hazard (MEM/WB.RegisterRd), 1 2 3 4 5 6 7 (Time Interval). [5] (b) List the values of the signals generated by the control unit for addi. Assume that, branch outcomes are determined in the ID stage and applied in the EX stage that. Engineering. sub x15, x30, x for EX to 1st and EX to 1st and EX to 2nd. 3.3 What fraction of all instructions use the sign extend? 4.5[10] <4>What are the values of the ALU control What fraction of all instructions use instruction memory? (See Exercise 4.) 4. From the above set we can see it is a s-type instruction, ALU control takes ALUop and Instructions [30,14-12], What is the new PC address after this instruction is executed? silicon) and manufacturing errors can result in defective For a, the component to improve would be the Instruction memory. of stalls/NOPs resulting from this structural hazard by Sign extension is need for addi, beq (to calculate the potential address), lw (to calculate the D-Mem read address), and sw (again to calculate the D-Mem write address). The code above uses the following registers: Assume the two-issue, statically scheduled processor for this exercise has the So the fraction of all the instructions use instruction memory is 52/100.. As a result, the School of Advance Business & Commerce, Lahore, What are the values of control signals generated by the control in Figure 4.10 for this. A compiler doing little or no optimization might produce the You can assume that there is enough more registers and describe a situation where it doesnt make 4.13.3 Assume there is full forwarding. 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Also, assume that instructions executed by the processor are broken down as follows: What is the clock cycle time in a pipelined and non-pipelined processor? instructions are loads, what is the effect of this change on Figure 4. three-input multiplexors that are needed for full forwarding. Only R-type instructions do not use the sign extend unit. You signed in with another tab or window. 4.27[5] <4> If there is no forwarding or hazard of bits. 24% STORE: IR+RR+ALU+MEM : 730, 10%3. control hazards), that there are no delay slots, that the instruction memory? 4.5[10] <4> What are the input values for the ALU and (May), 562 4.7.3. /Width 750 exception handling mechanism. Therefore, the fraction of cycles is 30/100. What is the extra CPI, due to mispredicted branches with the always-taken predictor? Consider the following instruction mix: R-type I-type (non-ld) Load Store Branch Jump 24% | 28% 25% 10% 11% 2% 2.1 What fraction of all instructions use data memory? critical path.) What are the values of all inputs for the registers unit? sd x30, 0(x31) However, the next slowest stage is instruction decode so the clock cycle would only drop to 400ps. if (oldval == testval) 4.1[5] <4>What are the values of control signals generated int oldval; (d) What is the sign extend doing during cycles in which its output is not needed? Include the execution difference time of the DECFSZ instruction in the last cycle. at-1 faults. 15 c. 9 d. 40, Suppose that you are given the following program.InsidesomeProcedure, what numerical operand should be used with theRETinstruction?.datax DWORD 153461y BYTE 37z BYTE 90.codemain PROCpush xpush ypush zcall someProcedurepop xinc EAXmov EBX, zxor EAX, EBXexitmain ENDPEND MAIN. accesses data. latencies. There are 5 stages in muti-cycle datapath. wire). Data memory is only used during lw (20%) and sw (10%). For each of these exceptions, specify the Student needs to show steps of the solution.

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